Target devices such as field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and structured ASICs are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of a large system often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) compilation flow are design generation and integration, synthesis, placement, and routing of the system on the target device.
System designs frequently implement a plurality of different processing channels. Processing channels may include the logic and routing used for performing one or more specific functions. Examples of processing channels include processors, controllers, filters, communication interfaces, and other devices. Processing channels may be implemented using pre-designed blocks of logic (intellectual property (IP) cores) or logic designed by a user.
Systems implemented on target devices operating in environments exposed to ionizing energies may be susceptible to faults. System upsets may range from a minor event such as erroneous data to catastrophic disruption of operation. In order to decrease error cross sections and satisfy safety critical requirements, redundancies may built in to provide for fault tolerance. Some systems provide for a duplicate of a critical processing channel where the outputs of the critical processing channels are compared to determine whether a fault has occurred.